1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming copper-based nitride liner/passivation layers for copper-based conductive structures, such as conductive lines/vias, that are formed on integrated circuit products.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements, such as transistors, capacitors, resistors, etc., to be formed on a given chip area according to a specified circuit layout. During the fabrication of complex integrated circuits using, for instance, MOS (Metal-Oxide-Semiconductor) technology, millions of transistors, e.g., N-channel transistors (NFETs) and/or P-channel transistors (PFETs), are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically includes doped source and drain regions that are formed in a semiconducting substrate and separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin gate insulation layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as the channel length of the transistor. Thus, in modern ultra-high density integrated circuits, device features, like the channel length, have been steadily decreased in size to enhance the performance of the semiconductor device and the overall functionality of the circuit. For example, the gate length (the distance between the source and drain regions) on modern transistor devices has been continuously reduced over the years and further scaling (reduction in size) is anticipated in the future. This ongoing and continuing decrease in the channel length of transistor devices has improved the operating speed of the transistors and integrated circuits that are formed using such transistors. However, there are certain problems that arise with the ongoing shrinkage of feature sizes that may at least partially offset the advantages obtained by such feature size reduction. For example, as the channel length is decreased, the pitch between adjacent transistors likewise decreases, thereby increasing the density of transistors per unit area. This scaling also limits the size of the conductive contact elements and structures, which has the effect of increasing their electrical resistance. In general, the reduction in feature size and increased packing density makes everything more crowded on modern integrated circuit devices, at both the device level and within the various metallization layers.
Improving the functionality and performance capability of various metallization systems has also become an important aspect of designing modern semiconductor devices. One example of such improvements is reflected in the increased use of copper metallization systems in integrated circuit devices and the use of so-called “low-k” dielectric materials (materials having a dielectric constant less than about 3) in such devices. Copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior metallization systems that used tungsten for the conductive lines and vias. The use of low-k dielectric materials tends to improve the signal-to-noise ratio (S/N ratio) by reducing crosstalk as compared to other dielectric materials with higher dielectric constants. However, the use of such low-k dielectric materials can be problematic as they tend to be less resistant to metal migration as compared to some other dielectric materials.
Copper is a material that is difficult to etch using traditional masking and etching techniques. Thus, conductive copper structures, e.g., conductive lines or vias, in modern integrated circuit devices are typically formed using known single or dual damascene techniques. In general, the damascene technique involves (1) forming a trench/via in a layer of insulating material, (2) depositing one or more relatively thin barrier or liner layers (e.g., TiN, Ta, TaN), (3) forming copper material across the substrate and in the trench/via, and (4) performing a chemical mechanical polishing process to remove the excess portions of the copper material and the barrier layer(s) positioned outside of the trench/via to define the final conductive copper structure. The copper material is typically formed by performing an electrochemical copper deposition process after a thin conductive copper seed layer is deposited by physical vapor deposition on the barrier layer.
Unfortunately, it is becoming more difficult to satisfy the ongoing demand for smaller and smaller conductive lines and conductive vias for a variety of reasons. One such problem with traditional barrier layer materials, e.g., tantalum, tantalum nitride, ruthenium, is the minimum thickness to which those materials must be formed so that they can be formed as continuous layers and perform their intended functions. Thus, having to make the barrier material a certain minimum thickness means that there is less room in the trench for the copper material. Accordingly, the overall resistance of the conductive structure increases, as the barrier layer material is less conductive than copper. Additionally, copper seed layers are typically formed to a thickness of about 5 nm to account for a portion of the seed layer will be oxidized, e.g., about 2-3 nm, between the time the copper seed layer is initially formed and the actual plating process. The additional thickness required for the copper seed layer also means that there is less room in the trench, thereby making filling operations more difficult. The presence of the oxidized seed layer may also lead to undesirable migration of oxygen in the surrounding structures.
The present disclosure is directed to various methods of forming copper-based nitride liner/passivation layers for copper-based conductive structures that may solve or at least reduce some of the problems identified above.